module pploadchk
(
input clk ,
input rst_n,
input [127:0] data,
input [31:4] data_addr,
input [31:2] data_req_addr,
input data_req,
output reg [31:0]resp_data,
output reg resp_v
);

always @ (posedge clk or negedge rst_n)
begin
    if(!rst_n)
        begin
            resp_data<=0;
            resp_v<=0;
        end
    else
        begin
            if(data_req && data_req_addr[31:4]==data_addr[31:4])
               begin
                    resp_v<=1;
                    resp_data<=(data_req_addr[3:2]==2'b00)?data[127:96]:
                               (data_req_addr[3:2]==2'b01)?data[95:64]:
                               (data_req_addr[3:2]==2'b10)?data[63:32]:
                               data[31:0];
               end
            else
                resp_v<=0;
        end
end

endmodule
